1. Field of the Invention
This invention relates to a power source means, and in particular, to a power source means which generates a pulse-width-modulated output voltage at the secondary side of a transformer in response to on-off operation of a main switching element in the primary side of the transformer at a duty ratio.
2. Related Art Statement
A switched-mode power source means, which generates a pulse-width-modulated output voltage at a transformer secondary side in response to on-off operation of the transformer primary side at a duty ratio, has been developed and is actually used extensively in electric apparatuses such as those employed for information processing and the like. The reason is that the switching circuit of such a power source means can be made small and has a high efficiency.
FIG. 5 shows a circuit diagram of a typical switched-mode power source means of the prior art. A direct current (DC) source 1 is connected across the primary winding 3a of a transformer 3 through a switch 2. A diode 4 and an output capacitor 5 are connected in series with the secondary winding 3b of the transformer 3, and a load 6 is connected in parallel with the output capacitor 5.
In the figure, black dots indicate the polarity of the windings 3a, 3b of the transformer 3. In operation, when the ON-OFF condition of the switch 2 is controlled, the following duty ratio D is also regulated, so that a pulse-width-modulated rectangular voltage is generated in the secondary winding 3b of the transformer 3 depending on the duty ratio D. EQU D=(ON time of switch 2)/(repetition period T)
The diode 4 rectifies the rectangular voltage, and the output capacitor 5 smooths the rectified output. If the voltage of the DC source 1 is represented by Ei and the voltage across the output capacitor 5, i.e., the output voltage, is represented by Eo, one can derive the following relationship. EQU Eo=(nEiD)/(1-D)
Where, n is the turn ratio between the primary and secondary windings of the transformer 3.
The above relationship between the DC source voltage Ei and the output voltage Eo holds only when the constituent devices of the circuit of FIG. 5, such as the switch 2, the diode 4 and the transformer 3 are of ideal nature and free from parasitic reactances. However, actual devices have inherent parasitic reactances, and the switching operation of the switch 2 inevitably generates noise. The generation of such noise will be described by referring to a case in which the switch 2 is a field effect transistor (FET).
FIG. 6 shows a power source means which is similar to the power source means of FIG. 5 except that the switch 2 is replaced by an FET 7, that the FET 7 and the diode 4 have parasitic capacitances 7a and 4a (such as several hundred pF.about.several ten nF), respectively, and that primary and secondary windings 3a and 3b of transformer have leakage inductances 3c, 3d of about several .mu.H, respectively. In particular, the parasitic capacitance 7a between the drain and source of FET 7 is of several tends of nF to several hundreds pF. The leakage inductances of the primary winding 3c and the secondary winding 3d of the transformer 3 arise in the order of several .mu.H.
When the FET 7 is ON, energy is stored in the leakage inductance 3c of the transformer 3 by the current through the FET 7 and the transformer primary winding 3a. As the FET 7 is turned OFF, the energy stored in the leakage inductance 3c is discharged through the drain-source parasitic capacitance 7a of the FET 7 in the form of a current therethrough, and an oscillation is caused between the leakage inductance 3c and the parasitic capacitance 7a. Similar oscillation is caused in the circuit of the leakage inductance 3d of the transformer 3 and the parasitic, capacitance 4a of the diode 4. FIG. 7A shows the resulting voltage oscillation across the FET 7, and FIG. 7B shows the resulting voltage oscillation across the diode 4.
The voltage oscillations, or surge voltages, due to the parasitic reactances sometimes are two to three times as high as the voltage Ei of the DC source, and such high surge voltages are harmful to switching elements and transformer windings. To prevent the occurrence of high surge voltages, elements for suppressing a quick change of voltage, such as snubber circuits made of serial circuits having resistors and capacitors, have been connected in parallel to the switching elements.
More specifically, one of the conventional methods for protecting elements from surge voltages accompanying the operation of the switching elements is to connect a gate resistor of several hundreds of ohms to the gate of the FET, so as to slow down the rise of gate voltage and to gradually reduce the drain-source resistance of the FET at the time of being turned ON. Such gate resistor suppresses the peak value of the surge current in the FET. Other examples of the conventionally used methods for protection against the surge voltage are connection of a saturable core in series with the FET and connection of snubber circuits or the like referred to above to the switching elements.
The conventional methods for protection against the surge voltage, however, have disadvantages in that the occurrence of surge voltages cannot be completely prevented, power consumption in the snubber circuits increases with on increase of the switching frequency and heat generation at the resistors of the snubber circuits increases accordingly.